In accordance with the increase in the integration of semiconductor memory devices, the area occupied by memory cells of a memory device has to be reduced to the minimum degree possible so as to increase the density of the device. Further, while the area occupied by the capacitor of the memory cell has to be minimized, the capacitance of the capacitor must be maintained over a certain value. Therefore, efforts are being made to increase the capacitance of the capacitor within a small area and limited space.
Particularly, in a DRAM cell consisting of one transistor and one capacitor, various capacitor structures have been proposed for application to 4 mega-bit, 16 mega-bit, and 256 mega-bit scale DRAM cells. A typical capacitor structure is constituted such that a V or U shaped trench is formed so as to utilize the wall of the trench as capacitor area. Another capacitor structure is the stacked type structure.
A conventional capacitor structure is described in a disclosure by Ahn Dae-Hyuk, published on Oct. 22, 1992, and entitled "Stacked Type Capacitor Structure and Formation Process Therefor". This reference will be briefly described referring to FIGS. 3 and 4. FIG. 3 is a layout of this structure, and FIG. 4 is a sectional view taken along the line X-Y-Z of FIG. 3.
The process for forming this conventional structure includes: a first step of forming device isolating oxide layer 41, source and drain regions 42 and 43, and word line electrodes 44, 45 and 46 on semiconductor substrate 40, then forming insulating layer 47 thereupon, and etching insulating layer 47 (formed on source region 42) so as to expose the surface of source region 42 and form a contact opening; a second step of forming bridge electrode layer 48 covering the upper surface of device isolating oxide layer 41 and the surface of source region 42 (exposed by the first contact opening), and forming polysilicon oxide layer 49 by a thermal oxidation process on the surface of bridge electrode layer 48; a third step of forming inter-layer insulating layer 50 on the whole surface of the substrate, and etching insulating layer 47 and inter-layer insulating layer 50 (formed on drain region 43) so as to expose the surface of drain region 43, and form a contact opening; forming bit line layer 51 on the whole surface of the substrate, forming a required pattern of bit line layer 51, forming inter-layer insulating layer 52 on the whole surface of the substrate, and sequentially etching inter-layer insulating layer 52 (over the relevant portions of bridge electrode layer 48), inter-layer insulating layer 50 and polysilicon oxide layer 49 so as to expose the relevant surfaces of bridge electrode layer 48 and form a contact opening; a fifth step of spreading polysilicon layer 54 on the whole surface of the substrate, doping a conduction-type impurity into polysilicon layer 54 and forming an electrode layer; and a sixth step of spreading dielectric layer 55 on the whole surface of the substrate to a certain thickness, and forming second polysilicon layer 56 upon dielectric layer 55.
The DRAM cell of this conventional technique includes: device isolating oxide layer 41 formed on the relevant portions of semiconductor substrate 40; source and drain regions 42 and 43; word line electrodes 44, 45 and 46; bridge electrode layer 48 having insulating layer 47 for covering word line electrodes 44, 45 and 46, for contacting with source region 42, and for covering the upper surface of device isolating oxide layer 41; bit line layer 51 contacting with drain region 43, and extending in parallel with the substrate surface upon bridge electrode layer 48; polysilicon layer 54 connected to bridge electrode layer 48 and extending over bit line layer 51; dielectric layer 55 covering the whole surface of the substrate including the upper surface of polysilicon layer 54; polysilicon layer 56 covering the upper surface of dielectric layer 55, and extending at least over bit line layer 51; and inter-layer isolating layers 50 and 52 for isolating bit line layer 51 from bridge electrode layer 48, polysilicon layer 54 and dielectric layer 55.
In the conventional technique as described above, as can be seen in the layout and in the sectional structure, bridge electrode layer 48 occupies a large area and a large space, but it cannot play the role of a capacitor, with the result that there is a limit in increasing the capacitance of the capacitor.